Get Advanced Computer Architecture: 10th Annual Conference, ACA PDF

By Junjie Wu, Haibo Chen, Xingwei Wang

ISBN-10: 3662444909

ISBN-13: 9783662444900

ISBN-10: 3662444917

ISBN-13: 9783662444917

This e-book constitutes the refereed court cases of the tenth Annual convention on complex laptop structure, ACA 2014, held in Shenyang, China, in August 2014. the nineteen revised complete papers offered have been rigorously reviewed and chosen from one hundred fifteen submissions. The papers are prepared in topical sections on processors and circuits; excessive functionality computing; GPUs and accelerators; cloud and information facilities; power and reliability; intelligence computing and cellular computing.

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Extra resources for Advanced Computer Architecture: 10th Annual Conference, ACA 2014, Shenyang, China, August 23-24, 2014. Proceedings

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D. Theorem 6. Let α be any memory order determined by the SRS model which satisfies the ordered pair condition. If in α, ∀ LˆSei a , Sˆ Sej a : value( LˆSei a) = value( Sˆ Sej a) , then ˆ Se < p S Se a < p LˆSe a , where i = j . ¬∃S Se j a : Sj a j i 38 H. Lyu, F. Zheng, and X. Xie Se Se Se Proof. If the theorem were false, then ∃S j a : Sˆ j a < p S j a < p LˆSei a . Again, according to Formula 2, it follows that Sˆ Sej a <α S Sej a . According to Formula 3, it follows that <α LˆSe <α S Se <α LˆSe S Se Sˆ Se j a j a j a i a .

Every multiplication needs 2 data at one time, but the bandwidth is limited. So the II has to increase to 3, which leads to performance degradation. In Hydro and Over cases, every iteration requires 3 data and writes one data. In the unlimited bandwidth condition, two iterations can be mapped into DSP-ACRP at one time, so the PP in bandwidth unlimited case of Hydro is 2. However, when the bandwidth is limited, only one iteration can be mapped at one time, so the PP in bandwidth limited case of Hydro decreases to 1.

Li Experiment We have implemented two ACRPs for DSP domain and secure hash algorithm, named DSP-ACRP and SHA-ACRP. The proposed reconfigurable architecture with the CFU has been designed at the RT-level with verilog. 13µm. ModelSim[17] is used for RTL-level and gate-level simulation. The simulation frequency is 100MHZ. We have applied several kernels of Livermore loops benchmark [18] and DSPstone [19] to the DSP-ACRP. And the MD5 and SHA algorithms in MiBench [20] are mapped to the SHA-ACRP. 1 Synthesis Results The DSP-ACRP contains 6 SPEs and 2 MAC-CFUs.

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Advanced Computer Architecture: 10th Annual Conference, ACA 2014, Shenyang, China, August 23-24, 2014. Proceedings by Junjie Wu, Haibo Chen, Xingwei Wang


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