By Muhammad S. Elrabaa
Advanced Low-Power electronic Circuit Techniques provides numerous novel excessive functionality electronic circuit designs that emphasize low-power and low-voltage operation. those circuits signify quite a lot of circuits which are utilized in state of the art VLSI platforms and for this reason function strong examples for low-power layout. every one bankruptcy incorporates a short creation that serves as a short history and provides the incentive in the back of the layout. each one bankruptcy additionally ends with a precis that in short explains the contributions contained therein. This makes the ebook very readable. The reader can skim in the course of the chapters in a short time to get a believe for the layout difficulties awarded within the booklet and the ideas proposed by means of the authors. Examples of circuits utilized in platforms the place low-power is necessary from reliability and portability issues of view (such as general-purpose and DSP processors) are awarded in Chapters 2, three and four. Chapters five and seven provide examples of circuits utilized in structures the place reliability and extra procedure integration are the most riding forces in the back of decreasing the ability intake. bankruptcy 6 offers an instance of a common goal high-performance low-power circuit layout.
Advanced Low-Power electronic Circuit Techniques is a true designer's publication. It investigates replacement circuit kinds, in addition to architectural choices, and provides quantitative effects for comparability in sensible applied sciences. numerous of the circuits awarded were fabricated in order that simulations could be checked. The circuits lined are crucial development blocks for plenty of designs, so the textual content might be of direct use to designers. MOS designs are coated, in addition to BiCMOS, and there are numerous novel circuits.
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Additional resources for Advanced Low-Power Digital Circuit Techniques
SC-25 , no. 2, pp . 388-394, April 1990.  M. 5-ns 32-b CMOS ALU in Double Pass-Transistor Logic", IEEE J. Solid-State Circuits, vol. SC-28, no. 11, pp. 1145-1151, November 1993. K . E. Swartzkander, "Estimating the Power Consumption of CMOS Adders", 11th IEEE Symposium on Computer Arithmetics, 1993, pp. 210-216.  C. , "Power-Delay Characteristics of CMOS Adders", IEEE Trans. on Very Large Scale Integration Systems, Vol. 3, Sept. 1994, pp. 377-381.  HSPICE Version H92, Meta-Software, Inc , 1992.
A comparison of th e various ar chitectures is also given. 3 th e circuit archite ct ure and simulat ion m ethod used is described. 7 the design and optimization of th e multiplier building block are discussed. 8 th e simulation results for a 6-bit modified Booth multiplier is pres ented. The impact and tradeoffs of the logic circuit style used is also discussed. 2 REVIEW OF PARALLEL MULTIPLIERS In this Section, several parallel multiplier algorithms whi ch have been used in VLSI are briefly presented.
1) '1 == ali' "%j ~ Yl3 Yll Y ........ g .... 2 Simulation Strategy Simulation of a complex circuit such as a 16xl6-bit multiplier is slow and difficult to use in the initial stages of the design process. 9), is a regular array of identical cells. It is therefore possible to replace most of the cells by their equivalent input capacitance and to study the performance of only a few of the basic building blocks under appropriate loading conditions. After the initial design is complete, a full simulation is then run to verify operation and obtain more accurate results.
Advanced Low-Power Digital Circuit Techniques by Muhammad S. Elrabaa